DESIGN OF CIRCULAR BUFFER AND LFSR

CIRCULAR BUFFER:

Verilog program

module buff(cell_3, cell_2, cell_1, cell_0, Data_in, clock, reset);

parameter buff_size = 4;

parameter word_size = 8;

output [word_size -1: 0] cell_3, cell_2, cell_1, cell_0;

input [word_size -1: 0] Data_in;

input clock,reset;

reg [buff_size -1: 0] Buff_Array [word_size -1: 0];

wire cell_3 = Buff_Array[3], cell_2 = Buff_Array[2];

wire cell_1 = Buff_Array[1], cell_0 = Buff_Array[0];

integer k;

always@(posedge clock)

begin

if (reset == 1)

for (k = 0; k <= buff_size -1; k = k+1)

Buff_Array[k] <= 0;

else

for (k = 1; k <= buff_size -1; k = k+1)

begin

Buff_Array[k] <= Buff_Array[k-1];

Buff_Array[0] <= Data_in;

end

end end module

LFSR:

module lfsr(clk, rst, load, shift, so);

input clk, rst, load, shift;

output [0:15]so;

reg [0:15] tmp;

wire lfsr_feedback = tmp[15]; //assign lfsr_feedback = tmp[15];

  always @(posedge clk)

    begin

    if (rst == 1'b1)

    tmp <= 16'b0000000000000000;           

    else     if(load == 1'b1 & shift == 1'b0)

    tmp <= 16'b1111111111111111;

    else     if(load == 1'b0 & shift == 1'b1)

begin

    tmp[0] <= lfsr_feedback;

    tmp[1] <= tmp[0];

    tmp[2] <= tmp[1];

    tmp[3] <= tmp[2] ^ lfsr_feedback;

    tmp[4] <= tmp[3] ^ lfsr_feedback;

    tmp[5] <= tmp[4] ^ lfsr_feedback;

    tmp[6] <= tmp[5];

    tmp[7] <= tmp[6];

    tmp[8] <= tmp[7];

    tmp[9] <= tmp[8];

    tmp[10] <= tmp[9];

    tmp[11] <= tmp[10];

    tmp[12] <= tmp[11];

    tmp[13] <= tmp[12];

    tmp[14] <= tmp[13];

    tmp[15] <= tmp[14];

  end   end

assign so = tmp; endmodule